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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>CINV -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CINV</h2>
      <p class="aml">Conditional Invert returns, in the destination register, the bitwise inversion of the value of the source register if the condition is TRUE, and otherwise returns the value of the source register.</p>
    <p>
        This is an alias of
        <a href="csinv.html">CSINV</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="csinv.html">CSINV</a>.
        </li><li>The description of <a href="csinv.html">CSINV</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">sf</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td colspan="5" class="lr">!= 11111</td><td colspan="4" class="lr">!= 111x</td><td class="lr">0</td><td class="lr">0</td><td colspan="5" class="lr">!= 11111</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td class="droppedname">op</td><td/><td colspan="8"/><td colspan="5" class="droppedname">Rm</td><td colspan="4" class="droppedname">cond</td><td/><td class="droppedname">o2</td><td colspan="5" class="droppedname">Rn</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (sf == 0)</span></h4><a id="CINV_CSINV_32_condsel"/><p class="asm-code">CINV  <a href="#sa_wd" title="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a>, <a href="#sa_wn_1" title="32-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Wn&gt;</a>, <a href="#sa_cond_1" title="Standard condition, excluding AL and NV (field &quot;cond&quot;)">&lt;cond&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="csinv.html#CSINV_32_condsel">CSINV</a> <a href="#sa_wd" title="32-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Wd&gt;</a>, <a href="#sa_wn_1" title="32-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Wn&gt;</a>, <a href="#sa_wn_1" title="32-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Wn&gt;</a>, invert(<a href="#sa_cond_1" title="Standard condition, excluding AL and NV (field &quot;cond&quot;)">&lt;cond&gt;</a>)</p>
          <p class="equivto">
          and is the preferred disassembly when
          <span class="pseudocode">Rn == Rm</span>.
        </p>
        </div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (sf == 1)</span></h4><a id="CINV_CSINV_64_condsel"/><p class="asm-code">CINV  <a href="#sa_xd" title="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a>, <a href="#sa_xn_1" title="64-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Xn&gt;</a>, <a href="#sa_cond_1" title="Standard condition, excluding AL and NV (field &quot;cond&quot;)">&lt;cond&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="csinv.html#CSINV_64_condsel">CSINV</a> <a href="#sa_xd" title="64-bit general-purpose destination register (field &quot;Rd&quot;)">&lt;Xd&gt;</a>, <a href="#sa_xn_1" title="64-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Xn&gt;</a>, <a href="#sa_xn_1" title="64-bit general-purpose source register (field &quot;Rn&quot; and &quot;Rm&quot;)">&lt;Xn&gt;</a>, invert(<a href="#sa_cond_1" title="Standard condition, excluding AL and NV (field &quot;cond&quot;)">&lt;cond&gt;</a>)</p>
          <p class="equivto">
          and is the preferred disassembly when
          <span class="pseudocode">Rn == Rm</span>.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wd&gt;</td><td><a id="sa_wd"/>
        
          <p class="aml">Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wn&gt;</td><td><a id="sa_wn_1"/>
        
          <p class="aml">Is the 32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xd&gt;</td><td><a id="sa_xd"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn&gt;</td><td><a id="sa_xn_1"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;cond&gt;</td><td><a id="sa_cond_1"/>
        
          <p class="aml">Is one of the standard conditions, excluding AL and NV, encoded in the "cond" field with its least significant bit inverted.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="csinv.html">CSINV</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1:</p>
    <ul>
      <li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
      <li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
    </ul>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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